The present invention relates to a multi-clock generator which is used in test equipment for logic ICs such as a microcomputer and which generates a preset number of clock pulses (multi-clock pulses) upon each input of a trigger clock.
In conventional IC test equipment for testing, for example, a semiconductor memory, one input data and one expected value data are generated for each clock from a timing generator and the input data is applied to an IC element under test, whose output is compared with the expected value data. That is, according to the prior art, one clock, one input data and one expected value data are generated for each test cycle which is commonly referred to as a rate. A series of such test patterns are prestored at successive addresses of a pattern memory, which is read out by advancing the address for each clock.
A logic circuit such as a microcomputer could also be tested by reading out a test pattern from the pattern memory in the same manner as described above. In the case of the microcomputer, it often happens that test data is subjected to a plurality of processing steps in the microcomputer, providing output data. In order to perform the plurality of processing steps in a sequential order, it is necessary to supply clocks of the same number as the steps one after another from the outside. Accordingly, in the pattern memory are stored the clocks at respective addresses and, at the same time, input data is stored at a certain address and expected value data is stored at an address spaced apart therefrom by the number of steps necessary for processing the input data. This inevitably increases the number of addresses of the pattern memory at which only the clocks are stored, resulting in an inefficient use of the pattern memory.